This invention relates generally to improving computer system efficiency, and more particularly to controlling restarting of instruction fetching using speculative address computations in conjunction with a recycle queue.
Pipeline restarts are very costly in today's highly pipelined microprocessors. One type of pipeline restart is due to instruction stream changes by taken branches. Pipelined microprocessors can include branch prediction logic that attempts to anticipate a branch target address. Due to limitations, the branch prediction logic may miss a prediction. These surprise (non-predicted) guess taken (SGT) branches are detected based on instruction text decoded later in the pipeline, requiring a flush and restart at the correct branch target address. Since the restart is dependent on the computation of the target address there can also be additional latency between the detection and restart point, further increasing the cycle per instruction (CPI) penalty. Modern pipelined microprocessors utilize branch prediction schemes to avoid these costly restart performance penalties. However, the efficient detection and resolution of SGT branches is still important, as there is an inherent “learning” period where the branch prediction logic primes branch target buffers (BTBs) to record branch addresses taken. This learning period is exposed at startup where a branch is encountered for the first time and also due to branch history capacity effects, where a learned branch may be removed and needs to be re-learned when later re-encountered.
In order to minimize the effect of these execution dependencies some microprocessors allow speculative execution in conjunction with a recycle mechanism. For example, speculation may be done on the result of data cache (D-Cache) accesses and addressing mode consistency. In cases where the speculation is incorrect, the operation/instruction is repeated/recycled. This allows a performance gain over always stalling the pipeline until the result (e.g., target address calculated utilizing D-Cache operand return) of an operation is known for certain, as in most cases the speculated result is correct. In such a scheme, the SGT target fetch is speculatively initiated as soon as a branch address is computed and later repeated/restarted if the branch is recycled. However, restarting instruction fetching on speculated address values can cause additional performance bottlenecks, as an instruction can be recycled multiple times before all speculations are resolved. Additionally, useful data in the instruction cache may be replaced with speculatively fetched data that may not actually be useful.
It would be beneficial to develop an approach to control restarting of instruction fetching using speculative address computations in a processor. Such an approach should limit repeated instruction fetching to cases where a wrong target value has been identified. Furthermore, modifications to higher levels of a cache memory hierarchy should be avoided when speculative instructions are not located in local cache. Accordingly, there is a need in the art for controlling restarting of instruction fetching using speculative address computations in a processor.